BELFEM 0.9.0
Berkeley Lab Finite Element Framework
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belfem::electronics::NgspiceCircuitFactory Class Reference

Builds an ElectricalCircuit from a lexed netlist ( todo/ngspice_parser_plan.md §9.2, decisions O5/O6/O8/O9 ). More...

#include <cl_NgspiceCircuitFactory.hpp>

Public Member Functions

 NgspiceCircuitFactory (const NetlistParser &aNetlist)
 build from a lexed netlist
 NgspiceCircuitFactory (const string &aPath)
 convenience: lex the file, then build
 ~NgspiceCircuitFactory ()
ElectricalCircuitcircuit ()
 hand the circuit over to the caller, who owns it from here; hard-errors on a second call
index_t node_index (const string &aName) const
 resolve a netlist node name ( case-folded; ground aliases "0"/"gnd" allowed ) to its BELFEM index – the O5 lookup for the deck-side terminal-pair and output readers.
uint number_of_nodes () const

Detailed Description

Builds an ElectricalCircuit from a lexed netlist ( todo/ngspice_parser_plan.md §9.2, decisions O5/O6/O8/O9 ).

Node map ( O9, frozen for restart ): the ground aliases "0" and "gnd" are one node and land on the LAST BELFEM index; every other node packs into 0 .. N-2 in order of first appearance in the netlist ( element cards and directive n+/n- keys alike ). A deck that never references ground is invalid ( manual, "Ground node" ). The map is logged at construction and exposed via node_index() so the deck-side terminal-pair reader resolves node NAMES through the same map ( O5 ) – never raw integers.

Components are created in netlist line order ( elements and directives merged by line ), which freezes the unknown-current layout for restart ( O9 ). Labels are the case-folded instance names ( O5 ).

v1 element support, refusals are hard errors naming the card:

  • R/C/L: value from the positional field or the r=/c=/l= keyword ( exactly one ); nonzero; ic= and every other keyword refused ( value-changing, plan §12.2 ). BDF order from the * belfem: order <instance> <n> directive ( O8 ), default 1, valid 1..6 ( the BDF kernel's own bound ).
  • V/I: bare value or DC <value> -> constant source; SIN(vo va freq [td theta phase]) -> sine, where vo/td/theta must be zero or absent ( BELFEM sine cannot represent them ); phase is in DEGREES per SPICE and converted to radians. PULSE/PWL/EXP/SFFM/AM are refused until Phase 6.
  • D: <model> referencing a .model <name> d(...) card; Is from is= ( default 1e-14 A per SPICE ), Vt = n * 0.026 V with n from the model ( default 1 ); any other model parameter, an area factor, or a non-d model type is refused.
  • directives: superconductor <name> n+= n-= Ic= n= Ec= length=, switch <name> n+= n-= state=open|closed t_switch=, order <instance> <n>; unknown kinds or keys are refused.

Ownership: the factory produces and hands over – circuit() transfers the ElectricalCircuit to the caller ( it can be called once ); an unclaimed circuit dies with the factory.

Constructor & Destructor Documentation

◆ NgspiceCircuitFactory() [1/2]

belfem::electronics::NgspiceCircuitFactory::NgspiceCircuitFactory ( const NetlistParser & aNetlist)

build from a lexed netlist

◆ NgspiceCircuitFactory() [2/2]

belfem::electronics::NgspiceCircuitFactory::NgspiceCircuitFactory ( const string & aPath)

convenience: lex the file, then build

◆ ~NgspiceCircuitFactory()

belfem::electronics::NgspiceCircuitFactory::~NgspiceCircuitFactory ( )
default

Member Function Documentation

◆ circuit()

ElectricalCircuit * belfem::electronics::NgspiceCircuitFactory::circuit ( )

hand the circuit over to the caller, who owns it from here; hard-errors on a second call

◆ node_index()

index_t belfem::electronics::NgspiceCircuitFactory::node_index ( const string & aName) const

resolve a netlist node name ( case-folded; ground aliases "0"/"gnd" allowed ) to its BELFEM index – the O5 lookup for the deck-side terminal-pair and output readers.

Hard-errors on a name the netlist does not contain.

◆ number_of_nodes()

uint belfem::electronics::NgspiceCircuitFactory::number_of_nodes ( ) const
inline

The documentation for this class was generated from the following files: